ATtiny167-ESSZ datasheet(48/282 Pages) ATMEL

48 / 282 page

7728D–AVR–07/09

ATtiny87/ATtiny167

• Bit5 - PRLIN: Power Reduction LIN / UART controller

Writing a logic one to this bit shuts down the LIN by stopping the clock to the module. When

waking up the LIN again, the LIN should be re initialized to ensure proper operation.

• Bit 4 - PRSPI: Power Reduction Serial Peripheral Interface

If using debugWIRE On-chip Debug System, this bit should not be written to one.

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock

to the module. When waking up the SPI again, the SPI should be re initialized to ensure

proper operation.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the

Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module in synchronous mode

(AS0 is 0). When the Timer/Counter0 is enabled, operation will continue like before the

shutdown.

• Bit 1 - PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When

waking up the USI again, the USI should be re-initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut

down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

ATtiny167-ESSZ Datasheet(PDF) 48 Page - ATMEL Corporation