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AT68166HT Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT68166HT Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 15 page  11 7843A–AERO–10/09 AT68166HT Read Cycle Table 5. Read cycle timings(1) Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode. 2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Wave- forms” on page 9.) Read Cycle 1. Address Controlled (CS = OE = VIL, WE = VIH) Read Cycle 2. Chip Select Controlled (WE = VIH) Symbol Parameter AT68166HT-25 AT68166HT-20 AT68166HT-18 (preliminary) Unit min max min max min max TAVAV Read cycle time 25 - 20 - 18 - ns TAVQV Address access time - 25 - 20 - 18 ns TAVQX Address valid to low Z 5 - 5 - 5 - ns TELQV Chip-select access time - 25 - 20 - 18 ns TELQX CS low to low Z(2) 5-5-5- ns TEHQZ CS high to high Z(2) -10- 9 - 9 ns TGLQV Output Enable access time - 12 - 10 - 9 ns TGLQX OE low to low Z(2) 2-2-2- ns TGHQZ OE high to high Z (2) -10- 9 - 9 ns ADDRESS DOUT CSx OE DOUT |
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