ADC0803 datasheet(35/41 Pages) NSC

35 / 41 page

Functional Description (Continued)

A flow chart for the zeroing subroutine is shown in

Figure 20.

It must be noted that the ADC0801 series will output an all

zero code when it converts a negative input [V

IN(−) ≥ VIN(+)].

Also, a logic inversion exists as all of the I/O ports are

buffered with inverting gates.

Basically, if the data read is zero, the differential output

voltage is negative, so a bit in Port B is cleared to pull V

more negative which will make the output more positive for

the next conversion. If the data read is not zero, the output

voltage is positive so a bit in Port B is set to make V

X more

positive and the output more negative. This continues for 8

approximations and the differential output eventually con-

verges to within 5 mV of zero.

The actual program is given in

Figure 21. All addresses used

are compatible with the BLC 80/10 microcomputer system.

In particular:

Port A and the ADC0801 are at port address E4

Port B is at port address E5

Port C is at port address E6

PPI control word port is at port address E7

Program Counter automatically goes to ADDR:3C3D upon

acknowledgement of an interrupt from the ADC0801

5.3 Multiple A/D Converters in a Z-80 Interrupt

Driven Mode

In data acquisition systems where more than one A/D con-

verter (or other peripheral device) will be interrupting pro-

gram execution of a microprocessor, there is obviously a

need for the CPU to determine which device requires servic-

ing.

Figure 22 and the accompanying software is a method

of determining which of 7 ADC0801 converters has com-

pleted a conversion (INTR asserted) and is requesting an

interrupt. This circuit allows starting the A/D converters in

any sequence, but will input and store valid data from the

converters with a priority sequence of A/D 1 being read first,

A/D 2 second, etc., through A/D 7 which would have the

lowest priority for data being read. Only the converters

whose INT is asserted will be read.

The key to decoding circuitry is the DM74LS373, 8-bit D type

flip-flop. When the Z-80 acknowledges the interrupt, the

program is vectored to a data input Z-80 subroutine. This

subroutine will read a peripheral status word from the

DM74LS373 which contains the logic state of the INTR

outputs of all the converters. Each converter which initiates

an interrupt will place a logic “0” in a unique bit position in the

status word and the subroutine will determine the identity of

the converter and execute a data read. An identifier word

(which indicates which A/D the data came from) is stored in

the next sequential memory location above the location of

the data so the program can keep track of the identity of the

data entered.

DS005671-92

FIGURE 19. Microprocessor Interface Circuitry for Differential Preamp

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