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MPC8535AVTATH Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc |
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MPC8535AVTATH Datasheet(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 126 page ![]() USB MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 63 2.11.1 USB DC Electrical Characteristics Table 46 provides the DC electrical characteristics for the USB interface. 2.11.2 USB AC Electrical Specifications Table 47 describes the general timing parameters of the USB interface of the MPC8535E. Figure 36 and Figure 37 provide the AC test load and signals for the USB, respectively. Figure 36. USB AC Test Load Table 46. USB DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2OVDD + 0.3 V Low-level input voltage VIL –0.3 0.8 V Input current IIN —±5 μA High-level output voltage, IOH = –100 μA VOH OVDD – 0.2 — V Low-level output voltage, IOL = 100 μA VOL —0.2 V Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. Table 47. USB General Timing Parameters Parameter Symbol 1 Min Max Unit Notes usb clock cycle time tUSCK 15 — ns 2-5 Input setup to usb clock - all inputs tUSIVKH 4 — ns 2-5 input hold to usb clock - all inputs tUSIXKH 1 — ns 2-5 usb clock to output valid - all outputs tUSKHOV — 7 ns 2-5 Output hold from usb clock - all outputs tUSKHOX 2 — ns 2-5 Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing (US) for the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. Output Z0 = 50 Ω OVDD/2 RL = 50 Ω |
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