AS3524 datasheet(75/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 56 DBOP control register

bits

Name

type

function

default

value

31:22

reserved

clr_pop_err

Interrupt clear signal for

pop error interrupt

Writing 1 to this bit will clear the pop

error interrupt. Writing 0 has no effect.

clr_push_err

Interrupt clear signal for

push error interrupt

Writing 1 to this bit will clear the push

error interrupt. Writing 0 has no effect

en_data

r/w

Tri-state enable for dout

bus

When set, dout bus is tri-stated when

there is no active write on the bus.

sdc

r/w

short count bit

res_even

r/w

reset to even cycle

when set, next output cycle is even

enw

r/w

enable write

0: write disabled

1: write enabled

strd

r/w

start read

14:13

osm

r/w

output serial mode

0: single word out

1: 2 serial words out

2: 4 serial words out

r/w

output data width

0: 8 bit data width

1: 16 bit data width

ir_enable

r/w

IR enable

0: all IR disabled

1: IR enabled

ir_po_err

r/w

IR enable on pop error

ir_pu_err

r/w

IR enable on push error

ir_e_en

r/w

IR enable set on push

empty

ir_ae_en

r/w

IR enable set on push

almost empty

ir_af_en

r/w

IR enabbe set on push

almost full

ir_f_en

r/w

IR enable set on push full

4:0

rs_t

r/w

read strobe time

0x1F

Notes:

If the start read bit is issued by setting the strd bit to 1, a single read cycle is generated. After this read cycle the strd

bit is set to 0 again by HW.

If write is enabled by setting enw=1, no read is possible (strd does not cause any action).

res_even is a reset bit that defines the start of even/odd generated signals. With res_even bit set, the next output

cycle is a even cycle. Within this first even output cycle the res_even bit is set to 0 by the SW.

sdc selects the counter length for the timing generator. Default is end value of 31. With sdc set to 1, the count end

value is 15.

en_data is used as a tri-state enable for the dout bus . When set as 1, dout is tri-stated if there is no active write on

the bus . When this bit is set as 0, dout is bus is tri-stated only during the read cycle.

AS3524 Datasheet(PDF) 75 Page - ams AG

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