MMA8450QT datasheet(39/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum

value depend on the ODR chosen (see Table 52).

In order to wake the device, the desired function or functions must be enabled and set to “Wake From Sleep”. All enabled

functions will still function in sleep mode at the sleep ODR. Only the functions that have been selected for “Wake From Sleep”

will wake the device.

MMA8450Q has 6 functions that can be used to keep the sensor from falling asleep namely, Transient, Orientation, Tap,

Motion/FF1 and Motion/FF2 and the FIFO. One or more of these functions can be enabled. In order to wake the device, functions

are provided namely, Transient, Orientation, Tap, and the two Motion/Freefall. Note that the FIFO does not wake the device. The

Auto-Wake/Sleep interrupt does not affect the wake/sleep, nor does the data ready interrupt. The FIFO gate (bit 7) in Register

0x3A, when set, will hold the last data in the FIFO before transitioning to a different ODR. After the buffer is flushed, it will accept

new sample data at the current ODR. See Register 0x3A for the wake from sleep bits.

If the Auto-Sleep bit is disabled, then the device can only toggle between Standby and Wake Mode by writing to the FS0 and

FS1 bits in Register 0x38 Ctrl Reg1. If Auto-Sleep interrupt is enabled, transitioning from Active mode to Auto-Sleep mode and

vice versa generates an interrupt.

0x38: CTRL_REG1 System Control 1 Register

It is important to note that when the device is in Auto-Sleep mode, the system ODR and the data rate for all the system

functional blocks are overwritten by the data rate set by the ASLP_RATE field in Register 0x38.

DR[2:0] bits select the output data rate (ODR) for acceleration samples. The default value is 000 for a data rate of 400 Hz.

Table 52. ASLP_COUNT Relationship with ODR

Output Data Rate (ODR)

Duration

Step

400

0 to 81s

320 ms

200

0 to 81s

320 ms

100

0 to 81s

320 ms

0 to 81s

320 ms

12.5

0 to 81s

320 ms

1.56

0 to 325.125s

640 ms

0x38 CTRL_REG1 Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ASLP_RATE1

ASLP_RATE0

DR2

DR1

DR0

FS1

FS0

Table 53. CTRL_REG1 Description

ASLP_RATE [1:0]

This register configures the Auto-Wake sample frequency when the device is in Sleep Mode.

See Table 54 for more information.

DR[2:0]

Data rate selection. Default value: 000

FS[1:0]

Full Scale selection. Default value: 00

(00: Standby mode; 01: active mode ±2g; 10: active mode ±4g; 11: active mode ±8g)

Table 54. Sleep Mode Poll Rate Description

ASLP_RATE1

ASLP_RATE0

Frequency (Hz)

12.5

1.56

Table 55. System Output Data Rate Selection

DR2

DR1

DR0

Output Data Rate (ODR)

Time Between Data Samples

400 Hz

2.5 ms

200 Hz

5 ms

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