STMPE811_09 datasheet(16/64 Pages) STMICROELECTRONICS

No. de pieza	STMPE811

Descripción Electrónicos	Advanced resistive touch screen controller with 8-bit GPIO expander

PDF	64 Pages

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Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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16 / 64 page

SPI interface

STMPE811

16/64

Doc ID 14489 Rev 2

5.2

SPI timing modes

The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the

"SDAT" and "A0" pins during power-up reset. The following four modes are defined

according to this setting.

The clocking diagrams of these modes are shown in ON reset. The device always operates

in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on

the next transaction defined by the CS_n pin being deasserted and asserted.

5.2.1

SPI timing definition

Table 9.

SPI timing modes

CPOL_N (SDAT pin)

CPOL

CPHA (ADDR pin)

Mode

100

101

010

011

Table 10.

SPI timing specification

Symbol

Description

Timing

Unit

Min

Typ

Max

tCSS

CS_n falling to

first capture

clock

−−

µs

tCL

Clock low

period

500

−−

tCH

Clock high

period

500

−−

tLDI

Launch clock

to MOSI data

valid

−−

tLDO

Launch clock

to MISO data

valid

−−

330

µs

tDI

Data on MOSI

valid

−−

µs

tCCS

Last clock

edge to CS_n

high

−−

µs

tCSH

CS_n high

period

−−

µs

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