EM351-RTR datasheet(89/240 Pages) ETC2

89 / 240 page

EM351 / EM357

8.4.6

Registers

Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA, SCx_SPICFG, and

SCx_SPISTAT registers.

8.5

TWI - Two Wire serial Interfaces

Both EM35x serial controllers SC1 and SC2 include a Two Wire serial Interface (TWI) master controller with the

following features:

Uses only two bidirectional GPIO pins

Programmable clock frequency (up to 400 kHz)

Supports both 7-bit and 10-bit addressing

Compatible with Philips’ I2C-bus slave devices

8.5.1

GPIO Usage

The TWI master controller uses just two signals:

SDA (Serial Data) – bidirectional serial data

SCL (Serial Clock) – bidirectional serial clock

Table 8-7 lists the GPIO pins used by the SC1 and SC2 TWI master controllers. Because the pins are configured

as open-drain outputs, they require external pull-up resistors.

Table 8-7. TWI Master GPIO Usage

SDA

SCL

Direction

Input / Output

GPIO Configuration

Alternate Output

(open drain)

Alternate Output

(open drain)

SC1 pin

PB1

PB2

SC2 pin

PA1

PA2

8.5.2

Set Up and Configuration

The TWI controller is enabled by writing 3 to the SCx_MODE register. The TWI controller operates only in

master mode and supports both Standard (100 kbps) and Fast (400 kbps) TWI modes. Address arbitration is not

implemented, so multiple master applications are not supported.

The TWI master controller’s serial clock (SCL) is produced by a programmable clock generator. SCL is

produced by dividing down 12 MHz according to this equation:

EXP

LIN

MHz

rate

)

(

8-18

120-035X-000D

Preliminary

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