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HCS12 Datasheet(PDF) 22 Page - Motorola, Inc |
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HCS12 Datasheet(HTML) 22 Page - Motorola, Inc |
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22 / 34 page ![]() Block Guide — S12BDM V4 22 Figure 4-1 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.(1) Figure 4-1 BDM Command Structure 4.6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see 3.1 BDM Status Register. This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide NOTES: 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See 4.6 BDM Serial Interface and 3.1 BDM Status Register for information on how serial clock rate is selected. HARDWARE HARDWARE FIRMWARE FIRMWARE GO, 44-BC BC = BUS CLOCK CYCLES COMMAND ADDRESS 150-BC DELAY NEXT DELAY 8 BITS AT ∼16 TC/BIT 16 BITS AT ∼16 TC/BIT 16 BITS AT ∼16 TC/BIT COMMAND ADDRESS DATA NEXT DATA READ WRITE READ WRITE TRACE COMMAND NEXT COMMAND DATA 64-BC DELAY NEXT COMMAND 150-BC DELAY 32-BC DELAY COMMAND COMMAND COMMAND COMMAND DATA NEXT COMMAND TC = TARGET CLOCK CYCLES |
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