TLK6002 datasheet(71/96 Pages) TI

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RXCLK_x

RDx

Tpd

VOH(ac)

VDDQ/2

VOL(ac)

VOH(ac)

VDDQ/2

VOL(ac)

RXCLK_x

RDx

tPERIOD

VOH(ac)

VDDQ/2

VOL(ac)

VOH(ac)

VDDQ/2

VOL(ac)

TPD

RXCLK_x

RDx

tPERIOD

VOH(ac)

VDDQ/2

VOL(ac)

VOH(ac)

VDDQ/2

VOL(ac)

TPD

TLK6002

www.ti.com

SLLSE34 – MAY 2010

Figure 4-13. HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements

4.11

HSTL Output Switching Characteristics (SDR Timing Mode Only)

PARAMETER

CONDITION

MIN

MAX

UNIT

Tduty

RXCLK_x(1) Duty Cycle

Rising and Falling Edge Aligned Data(2)

40%

60%

tperiod

RXCLK_x Period

Rising and Falling Edge Aligned Data

3.2

42.55

Tfreq

RXCLK_x Frequency

Rising and Falling Edge Aligned Data

23.5

312.5

MHz

RXCLK_x rising to RDx(3) valid.

Rising Edge Aligned, See Figure 4-14.(2)

–0.10 ×

+0.10 ×

tperiod

Tpd

RXCLK_x falling to RDx valid.

Falling Edge Aligned, See Figure 4-15.(2)

–0.10 ×

+0.10 ×

tperiod

(1)

RXCLK_x refers to RXCLK_A or RXCLK_B for channels A and B respectively.

(2)

Cload = 10pF, using timing reference of (VDDQA/B)/2.

(3)

RDx refers to either RDA or RDB for channels A and B respectively.

Figure 4-14. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements

Figure 4-15. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements

ELECTRICAL SPECIFICATIONS

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