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74ALVT16601DGG Datasheet(PDF) 13 Page - NXP Semiconductors |
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74ALVT16601DGG Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 20 page ![]() 74ALVT16601_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 5 July 2005 13 of 20 Philips Semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 12. Waveforms Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable (LEAB, LEBA) pulse width Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Propagation delay clock input (CPAB, CPBA) to output (An, Bn), clock pulse width (CPAB, CPBA) and maximum clock frequency (CPAB, CPBA) 001aad308 output Bn or An input An or Bn VM VM tPHL tPLH VM VM VOH VI 0 V VOL 001aad310 VM VM VM VM VM tPLH tPHL tWH input LEAB or LEBA output An or Bn VOH VOL VI 0 V 001aad254 VM VM VM VM VM tPLH tPHL tWL tWH input CPBA or CPAB output An or Bn 1/fmax VOH VI VOL 0 V |
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