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4-217
RF2365
Rev A4 001201
4
Pin
Function
Description
Interface Schematic
1RF IN
RF input pin. This pin is DC coupled.
2GND1
Ground connection. See evaluation board schematic notes.
3PD
Power down pin. This pin serves as the interstage for the 2-stage LNA.
An inductor is required to pull pin 3 to VCC (see application schematic).
If desired, this voltage can be lowered to trade off IP3 versus ICC,TOTAL.
(See table below.)
4GND2
Ground connection. See evaluation board schematic notes.
5RF OUT
Amplifier Output pin. This pin is an open-collector output. It must be
biased to either VCC or pin 4 through a choke or matching inductor.
This pin is typically matched to 50
Ω with a shunt bias/matching induc-
tor and series blocking/matching capacitor. Refer to application sche-
matics.
R1
IIP3
ICC
0
Ω
+4.0dBm
8.0mA
75
Ω
+2.0dBm
6.5mA
150
Ω
-3.5dBm
5.0mA
GND1
RF IN
PD
To Bias
Circuit
PD
To RF
Stages
To Bias
Circuit
GND2
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