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SC643 Datasheet(PDF) 16 Page - Semtech Corporation

No. de pieza SC643
Descripción Electrónicos  Light Management Unit with 4 LDOs and SemPulse짰Interface
PDF  26 Pages
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Fabricante Electrónico  SEMTECH [Semtech Corporation]
Página de inicio  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC643 Datasheet(HTML) 16 Page - Semtech Corporation

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SC643
16
Applications Information (continued)
PCB Layout Considerations
The layout diagram in Figure 2 illustrates a proper two-
layer PCB layout for the SC643 and supporting
components. Following fundamental layout rules is
critical for achieving the performance specified in the
Electrical Characteristics table. The following guidelines
are recommended when developing a PCB layout:
Place all bypass and decoupling capacitors —
C1, C2, CIN, COUT, CLDO1, CLDO2, CLDO3,
CLDO4, and CBYP as close to the device as
possible.
All charge pump current passes through IN,
OUT, and the bucket capacitor connection pins.
Ensure that all connections to these pins make
use of wide traces so that the resistive drop on
each connection is minimized.
The thermal pad should be connected to the
ground plane using multiple vias to ensure
proper thermal connection for optimal heat
transfer.
The following capacitors — CLDO1, CLDO2,
CLDO3, CLDO4, and CBYP should be grounded
together. Connect these capacitors to the
ground plane at one point near the AGND pin
as shown in Figure 2.
Figure 3 shows the pads that should be con-
nected to the ground plane with multiple vias.
Make all ground connections to a solid ground
plane as shown in Figure 4.
If a ground layer is not feasible, the following
groupings should be connected:
PGND — CIN, COUT
AGND — Ground Pad, CLDO1, CLDO2,
CLDO3, CLDO4, CBYP
If no ground plane is available, PGND and AGND
should be routed back to the negative battery
terminal, separately, using thick traces. Joining
the two ground returns at the terminal prevents
large pulsed return currents from mixing with
the low-noise return currents of the LDOs.
All LDO output traces should be made as wide
as possible to minimize resistive losses.
Figure 2 — Recommended PCB Layout
Figure 3 — Layer 1
Figure 4 — Layer 2
COUT
C1
C2
BL2
BL1
LDO1
LDO2
BYP
IN
LDO3
VIN
VOUT
SC643
BL3
PGND
CLDO1
AGND
PGND
SPIF
CLDO3
CLDO4
CLDO2
CBYP
CIN
PGND
PGND
Ground Plane



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