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AD9550

Rev. 0 | Page 16 of 20

Output Dividers

The output divider section consists of three dividers: P0, P1, and P2.

The P0 divider (or VCO frequency prescaler) accepts the VCO

frequency and reduces it by an integer factor of 5 to 11, thereby

reducing the frequency to a range between 305 MHz and 810 MHz.

The output of the P0 divider independently drives the P1 divider

and the P2 divider. The P1 divider establishes the frequency at

OUT1 and the P2 divider establishes the frequency at OUT2.

The P1 and P2 dividers are each programmable over a range of

1 to 1023, which results in a frequency at OUT1 or OUT2 that

is an integer submultiple of the frequency at the output of the

P0 divider.

Output Driver Mode Control

Three mode control pins (OM0, OM1, and OM2) establish the

logic family and pin function of the output drivers. The logic

families include LVDS, LVPECL, and CMOS (see Table 10).

Table 10. Logic Family Assignment via the OMx Pins

Pin OMx

Logic Family

OUT1

OUT2

000

LVPECL

001

LVPECL

LVDS

010

LVDS

LVPECL

011

LVPECL

CMOS

100

LVDS

101

LVDS

CMOS

110

CMOS

LVDS

111

CMOS

Because both output drivers support the LVDS and LVPECL

logic families, each driver has two pins to handle the differential

signals associated with these two logic families. The OUT1 driver

uses the OUT1 and OUT1 pins, and the OUT2 driver uses the

OUT2 and OUT2 pins. When the OMx pins select the CMOS

logic family, the signal at the OUT1 pin is a phase aligned replica

of the signal at the OUT1 pin and the signal at the OUT2 pin is a

phase aligned replica of the signal at the OUT2 pin.

JITTER TOLERANCE

Jitter tolerance is the ability of the AD9550 to maintain lock in the

presence of sinusoidal jitter. The AD9550 meets the input jitter

tolerance mask per Telcordia GR-253-CORE (see Figure 25).

The acceptable jitter tolerance is the region above the mask.

0.1

100

1000

0.1

0.01

100

10M

JITTER FREQUENCY (kHz)

AD9550

MASK

Figure 25. Jitter Tolerance

LOW DROPOUT (LDO) REGULATORS

The AD9550 is powered from a single 3.3 V supply and contains

on-chip LDO regulators for each function to eliminate the need

for external LDOs. To ensure optimal performance, each LDO

output should have a 0.47 μF capacitor connected between its

access pin and ground.

AUTOMATIC POWER-ON RESET

The AD9550 has an internal power-on reset circuit (see Figure 26).

At power-up, an 800 pF capacitor momentarily holds a Logic 0 at

the active low input of the reset circuitry. This ensures that the

device is held in a reset state (~250 µs) until the capacitor charges

sufficiently via the 100 kΩ pull-up resistor and 200 kΩ series

resistor. Note that when using a low impedance source to drive

the RESET pin, be sure that the source is either tristate or Logic 0

at power-up; otherwise, the device may not calibrate properly.

RESET

200k

Ω

100k

Ω

800pF

VDD

RESET

CIRCUITRY

AD9550

Figure 26. Power-On Reset

Provided an input reference signal is present at the REF pin, the

device automatically performs a VCO calibration during power-up.

If the input reference signal is not present, VCO calibration fails

and the PLL does not lock. As soon as an input reference signal

is present, the user must reset the device to initiate the automatic

VCO calibration process.

Any change to the preset frequency selection pins requires the

user to reset the device. This is necessary to initiate the automatic

VCO calibration process.

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