FS8108

Page 9

Jan 2003

Quick-lock Signal (DB)

The quick-lock output signal, DB, is provided so that the PLL may achieve higher speed

locking. When connected, the DB output effectively doubles the charge pump current out-

put to the loop filter during the initial start-up of the PLL (when OPR first goes high).

Once the PLL phase error is within a specific tolerance, the quick-lock circuitry sets the

DB output to a high impedance state and the PLL continues toward lock with its normal

charge pump current.

Stand-by Mode

The stand-by mode for the PLL is entered by setting the OPR pin low and V

while the circuit is in operation. In the stand-by mode, the XIN and FIN amplifiers, N-

counter, and R-counter are stopped, the N- and R-counters are also reset, and the DO and

DB outputs are set to the high impedance state. As long as voltage is supplied to V

data loaded to the latches is kept. To exit from stand-by mode to normal operation, the

OPR pin must be set high and voltage must again be supplied to V