ATSAM3S4AA-MU datasheet(52/65 Pages) ATMEL

52 / 65 page

6500AS–ATARM–11-Dec-09

SAM3S Summary

• Programmable gain: 1, 2, 4

12.11 Digital-to-Analog Converter (DAC)

• Up to 2 channel 12-bit DAC

• Up to 2 mega-samples conversion rate in single channel mode

• Flexible conversion range

• Multiple trigger sources for each channel

• 2 Sample/Hold (S/H) outputs

• Built-in offset and gain calibration

• Possibility to drive output to ground

• Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H

stage)

• Two PDC channels

• Power reduction mode

12.12 Static Memory Controller

• 16-Mbyte Address Space per Chip Select

• 8- bit Data Bus

• Word, Halfword, Byte Transfers

• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

• Programmable Data Float Time per Chip Select

• External Wait Request

• Automatic Switch to Slow Clock Mode

• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

• NAND FLASH additional logic supporting NAND Flash with Multiplexed Data/Address buses

• Hardware Configurable number of chip select from 1 to 4

• Programmable timing on a per chip select basis

12.13 Analog Comparator

• One analog comparator

• High speed option vs. low power option

• Selectable input hysteresis:

– 0, 20 mV, 50 mV

• Minus input selection:

– DAC outputs

– Temperature Sensor

–ADVREF

– AD0 to AD3 ADC channels

• Plus input selection:

– All analog inputs

ATSAM3S4AA-MU Datasheet(PDF) 52 Page - ATMEL Corporation