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PIP202-12M-2 Datasheet(PDF) 11 Page - NXP Semiconductors

No. de pieza PIP202-12M-2
Descripción Electrónicos  DC-to-DC converter powertrain
PDF  20 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

PIP202-12M-2 Datasheet(HTML) 11 Page - NXP Semiconductors

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Philips Semiconductors
PIP202-12M-2
DC-to-DC converter powertrain
Product data
Rev. 02 — 24 November 2003
11 of 20
9397 750 11943
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
To protect the control circuit from the transient voltages, the following precautions
must be taken. Refer to Figure 12.
1. The output stage ground (VSSO) must be connected to the decoupling capacitor
(Cin) before joining the ground plane. Otherwise, the switching noise on VSSO will
couple into the control circuit ground (VSSC).
2. The control circuit supply must be filtered using a resistor-capacitor (RC) filter.
The values shown in Figure 12 are suitable for most applications.
3. It is essential that the VSSC (signal ground) connection at the device is not
connected in the current return path between the VSSO (power ground)
connection at the device and the VDDO input capacitor.
4. It is also essential that the input to the VDDC (logic power) filter is not connected in
the current path between the VDDO (conversion power) connection at the device.
11.4 Switching frequency
A high operating frequency reduces the size and number of capacitors needed to
filter the output current, and also reduces the size of the output inductors. The
disadvantage, however is higher dissipation due to switching and MOSFET driver
losses. For example, doubling the operating frequency of the circuit in Figure 11 from
500 kHz to 1 MHz would increase the power dissipation in each PIP202-12M from
4 W to 6 W, at an output current of 20 A in each PIP202-12M.
The maximum switching frequency is limited by thermal considerations, the
dissipation in the PIP202-12M device(s) and the thermal resistance from junction to
ambient.
11.5 Thermal design
The PIP202-12M has three pads on its underside. These are designated PAD1, PAD2
and PAD3 (Figure 2). PAD1 is connected to VDDO, PAD2 is connected to VSSC and
PAD3 is connected to VO. In addition to providing low inductance electrical
connections, these pads conduct heat away efficiently from the MOSFETs and
control IC to the printed-circuit board. The thermal resistance from junction to
printed-circuit board is approximately 5 K/W. In order to take full advantage of the low
Fig 12. External connection of power and signal lines.
VI
VDDC
VSSC
VO
VDDO
control circuit
supply (12 V)
output stage supply voltage
VSSO
CB
03ae27
output
100
nF
Lout
Cout
10
1
µF
Cin
signal ground
power ground
input voltage
from PWM controller



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