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PCA8802B Datasheet(PDF) 21 Page - NXP Semiconductors |
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PCA8802B Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 34 page ![]() PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 21 of 34 NXP Semiconductors PCA8802 Smartcard RTC [1] Unless otherwise defined, IDD is measured with the reset state, see Section 9.7. [2] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: . 12. Dynamic characteristics [1] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [2] Rise and fall times are not limited. Fast edges may lead to system EMI problems, whilst slow edges are susceptible to noise. IOL LOW-level output current VOL = 1.0 V; VDD =5V; on pins INT and SDA −2 −7- mA VOL = 0.32 V; VDD = 1.6 V; on pins INT and SDA −0.4 −1- mA ILO output leakage current VO =VDD or VSS; on pins SDA and INT −200 0 +200 nA Table 11. Static characteristics …continued VDD = 1.6 V to 5.5 V; VSS =0V; fosc = 32.768 kHz; Tamb = −40 °C to +85 °C; quartz crystal: Rs =30kΩ, CL = 6.0 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit C Litg () C OSCI C OSCO ⋅ () C OSCI C OSCO + () -------------------------------------------- = Table 12. Dynamic characteristics VDD = 1.6 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. [1] Symbol Parameter Conditions Min Typ Max Unit Timing characteristics: serial bus fSCL SCL clock frequency - - 1 MHz tLOW LOW period of the SCL clock 500 - - ns tHIGH HIGH period of the SCL clock 260 - - ns tBUF bus free time between a STOP and START condition 500 - - ns tHD;STA hold time (repeated) START condition 260 - - ns tSU;STA set-up time for a repeated START condition 260 - - ns tr rise time of both SDA and SCL signals [2] -10 - ns tf fall time of both SDA and SCL signals [2] -10 - ns tSU;DAT data set-up time 50 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 260 - - ns tVD;DAT data valid time 75 - 450 ns Cb capacitive load for each bus line - - 50 pF Timing characteristics: INT tw(int) interrupt pulse width 20 40 80 µs |
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