M95128-WDW3GSLASHPC datasheet(18/44 Pages) STMICROELECTRONICS

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Instructions

M95128, M95128-W, M95128-R

18/44

Doc ID 5798 Rev 13

5.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

sending the instruction code followed by the data byte on Serial Data input (D), and driving

the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of

Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge

of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not

executed.

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-

timed write cycle that takes tW to complete (as specified in Table 16, Table 17, Table 19 and

Table 19). The instruction sequence is shown in Figure 8.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write

cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also

reset at the end of the write cycle tW.

The Write Status Register (WRSR) instruction allows the user to change the values of the

BP1, BP0 and SRWD bits:

●

The Block protect (BP1, BP0) bits define the size of the area that is to be treated as

read only, as defined in Table 5.

●

The SRWD bit (Status register write disable bit), in accordance with the signal read on

the Write protect pin (W), allows the user to set or reset the write protection mode of the

Status Register itself, as shown in Table 5. When in the Write-protected mode, the

Write Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the

WRSR instruction, including the tW write cycle.

The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0

bits in the Status Register. Bits b6, b5, b4 are always read as 0.

Table 5.

Protection modes

signal

SRWD

bit

Mode

Write protection of the

Status Register

Memory content

Protected area(1)

As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.

Unprotected area(1)

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the BP1

and BP0 bits can be

changed

Write Protected

Ready to accept Write

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the BP1

and BP0 bits cannot be

changed

Write Protected

Ready to accept Write

instructions

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