AD9552

Rev. C | Page 28 of 32

OUT1 Driver Control (Register 0x32)

Table 24.

Address

Bit

Bit Name

Description

0x32

7

OUT1 drive strength

Controls the output drive capability of the OUT1 driver.

0 = weak.

1 = strong (default).

6

OUT1 power-down

Controls power-down functionality of the OUT1 driver.

0 = OUT1 active (default).

1 = OUT1 powered down.

[5:3]

OUT1 mode control

OUT1 driver mode selection.

000 = CMOS, both pins active.

001 = CMOS, positive pin active, negative pin tristate.

010 = CMOS, positive pin tristate, negative pin active.

011 = CMOS, both pins tristate.

100 = LVDS.

101 = LVPECL (default).

110 = not used.

111 = not used.

[2:1]

OUT1 CMOS polarity

Selects the polarity of the OUT1 pins in CMOS mode.

00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default).

01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0.

10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1.

11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0.

These bits are ineffective unless Bits[5:3] select CMOS mode.

0

Enable SPI control of OUT1

driver control

Controls OUT1 driver functionality.

0 = OUT1 is LVDS or LVPECL, per the OUTSEL pin (Pin 15) (default).

1 = OUT1 functionality defined by Bits[7:1].

Select OUT2 Source Control (Register 0x33)

Table 25.

Address

Bit

Bit Name

Description

0x33

[7:4]

Unused

Unused.

3

OUT2 source

Selects the signal source for OUT2.

1 = source for OUT2 is the input reference (REF or XTAL).

[2:0]

Unused

Unused.