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MPC8572ECLPXAVND Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc |
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MPC8572ECLPXAVND Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc |
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98 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 98 Freescale Semiconductor Serial RapidIO 17.7 Receiver Eye Diagrams For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding Bit Error Rate specification (Table 71,Table 72, and Table 73) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver Input Compliance Mask shown in Figure 60 with the parameters specified in Table 74. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100- Ω +/– 5% differential resistive load. Figure 60. Receiver Input Compliance Mask 17.8 Measurement and Test Requirements Because the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided Table 74. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter Receiver Type VDIFFmin (mV) VDIFFmax (mV) A (UI) B (UI) 1.25 GBaud 100 800 0.275 0.400 2.5 GBaud 100 800 0.275 0.400 3.125 GBaud 100 800 0.275 0.400 1 0 VDIFF max -VDIFF max VDIFF min -VDIFF min Time (UI) 0 AB 1-B 1-A |
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