MPC8572ECLPXATLD datasheet(12/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Electrical Characteristics

2.1.2

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for this device. Note that the values shown are the

recommended and tested operating conditions. Proper device operation outside these conditions is not

guaranteed.

Table 2. Recommended Operating Conditions

Characteristic

Symbol Recommended Value Unit Notes

Core supply voltage

VDD

1.1 V ± 55 mV

—

PLL supply voltage

AVDD

1.1 V ± 55 mV

Core power supply for SerDes transceivers

SVDD

1.1 V ± 55 mV

—

Pad power supply for SerDes transceivers

XVDD

1.1 V ± 55 mV

—

DDR SDRAM

Controller I/O

supply voltage

DDR2 SDRAM Interface

GVDD

1.8 V ± 90 mV

—

DDR3 SDRAM Interface

1.5 V ± 75 mV

—

Three-speed Ethernet I/O voltage

LVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

TVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

DUART, system control and power management, I2C, and JTAG I/O voltage

OVDD

3.3 V ± 165 mV

Local bus and GPIO I/O voltage

BVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

1.8 V ± 90 mV

V—

Input voltage

DDR2 and DDR3 SDRAM Interface signals

MVIN

GND to GVDD

DDR2 and DDR3 SDRAM Interface reference

MVREFn

GVDD/2 ± 1%

—

Three-speed Ethernet signals

LVIN

TVIN

GND to LVDD

GND to TVDD

Local bus and GPIO signals

BVIN

GND to BVDD

V—

Local bus, DUART, SYSCLK, Serial RapidIO, system

control and power management, I2C, and JTAG

signals

OVIN

GND to OVDD

Junction temperature range

0 to 105

°C—

Notes:

1. This voltage is the input to the filter discussed in Section 21.2.1, “PLL Power Supply Filtering,” and not necessarily the

voltage at the AVDD pin, that may be reduced from VDD by the filter.

2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

MPC8572ECLPXATLD Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc

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