Philips Semiconductors

PCKEL14

2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip

Product data

Rev. 01 — 14 October 2002

7 of 15

9397 750 09564

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

[1]

Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in

a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.

[2]

[3]

Outputs are terminated through a 50

Ω resistor to V

[4]

differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies

Table 7:

Negative DC characteristics[1]

Symbol Parameter

Conditions

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

power supply

current

-

3240-

32

40

-

3442mA

HIGH-level

output voltage

[3]

−1175 −1040 −880 −1065 −955 −880 −1025 −955 −880 mV

LOW-level

output voltage

[3]

−1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV

HIGH-level input

voltage

single-ended

−1190 -

−880 −1165 -

−880 −1165 -

−880 mV

LOW-level input

voltage

single-ended

−1810 -

−1475 −1810 -

−1475 −1810 -

−1475 mV

output voltage

reference

−1.43 -

−1.25 −1.35 -

−1.25 −1.35 -

−1.19 V

HIGH-level input

voltage,

common mode

range

(differential)

-

−0.4

−2.1

-

−0.4

−2.1

-

−0.4

V

−1.8

-

−0.4

−1.9

-

−0.4

−1.9

-

−0.4

V

HIGH-level input

current

-

-

150

-

-

150

-

-

150

µA

LOW-level input

current

CLK

−300 -

-

−300 -

-

−300 -

-

µA

others

0.5

-

-

0.5

-

-

0.5

-

-

µA