AD21462WBBZ3 datasheet(13/60 Pages) AD

13 / 60 page

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Rev. PrA

Page 13 of 60

November 2008

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 6:

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 6. Pin List

Name

Type

LVTTL SSTL18

State

During

and After

Reset

Description

AMI_ADDR23–0

I/O/T

High-Z/

driven low

(boot)

External Address. The ADSP-21462W/ADSP-21465W/ADSP-21467 outputs

addresses for external memory and peripherals on these pins. The data pins

can be multiplexed to support the PDAP (I) and PWM (O). After reset, all

AMI_ADDR23-0 pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS

mode (default). When configured in the IDP_PDAP_CTL register, IDP

channel 0 scans the AMI_ADDR23–0 pins for parallel input data.

AMI_DATA7–0

I/O/T

High-Z

External Data. The data pins can be multiplexed to support the external

memory interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset,

all AMI_DATA pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS mode

(default).

DAI _P20–1

I/O with fixed weak

pull-up on input

path 1, 2

High-Z

Digital Applications Interface Pins. These pins provide the physical

interface to the DAI SRU. The DAI SRU configuration registers define the com-

bination of on-chip audiocentric peripheral inputs or outputs connected to

the pin and to the pin’s output enable. The configuration registers of these

peripherals then determine the exact behavior of the pin. Any input or output

signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports, the S/PDIF module, input data

ports (2), and the precision clock generators (4), to the DAI_P20–1 pins.

DPI _P14–1

I/O with fixed weak

pull-up only on

input path1, 2

High-Z

Digital Peripheral Interface. These pins provide the physical interface to the

DPI SRU. The DPI SRU configuration registers define the combination of on-

chip peripheral inputs or outputs connected to the pin and to the pin’s output

enable. The configuration registers of these peripherals then determines the

exact behavior of the pin. Any input or output signal present in the DPI SRU

may be routed to any of these pins. The DPI SRU provides the connection from

the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to the

DPI_P14–1 pins.

AMI_ACK

I (pu)

Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK

(low) to add wait states to an external memory access. AMI_ACK is used by I/O

devices, memory controllers, or other peripherals to hold off completion of

an external memory access.

AMI_RD

O/T

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-

21462W/ADSP-21465W/ADSP-21467 reads a word from external memory.

AMI_RD has fixed internal pull-up resistor1, 2.

AMI_WR

O/T

High-Z

External Port Write Enable. AMI_WR is asserted when the ADSP-

21462W/ADSP-21465W/ADSP-21467 writes a word to external memory.

AMI_WR has fixed internal pull-up resistor1, 2.

DDR2_ADDR15–0

O/T

High-Z/

Driven low

DDR2 Address pins. DDR2 address pins.

DDR2_BA2-0

O/T

High-Z/

Driven low

DDR2 Bank Address Input pins. Define which bank an ACTIVATE,

READ, WRITE, or PRECHARGE command is being applied. BA2–0

define which mode register including MR, EMR, EMR(2), and

EMR(3) is loaded during the LOAD MODE command.

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