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L6460 Datasheet(PDF) 28 Page - STMicroelectronics

No. de pieza L6460
Descripción Electrónicos  SPI configurable stepper and DC multi motor driver
PDF  139 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6460 Datasheet(HTML) 28 Page - STMicroelectronics

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Electrical specifications
L6460
28/139
Doc ID 17713 Rev 1
IAD
A/D path absorbed current
ADChannelX[4:0]
=10001 and
bit EnDacScale=0
-1
1
µA
tDELAY
Delay from serial write to pin
low
CLOAD =50 pF
(45)
500
ns
SPI interface (40)
VIH
High level input voltage
(46)
1.6
V
VIL
Low level input voltage
(46)
0.8
V
VHYS
Input voltage hysteresis
(46)
0.15
0.22
V
VOH
High level output voltage
IOUT = -10mA,
(47)
2.75
V
VOL
Low level output voltage
IOUT = 10mA,
(47)
0.4
V
tSCLK
SCLK period
62.5
ns
tSCLK_rise
SCLK rise time
2
ns
tSCLK_fall
SCLK fall time
2
ns
tSCLK_high
SCLK high time
20
ns
tSCLK_low
SCLK low time
20
ns
tnSS_setup
nSS setup time
10
ns
tnSS_hold
nSS hold time
10
ns
tnSS_min
nSS high minimum time
30
ns
tMOSI_setup
MOSI setup time
10
ns
tMOSI_hold
MOSI hold time
10
ns
tMISO_rise
MISO rise time
CLOAD=50pF
(48)
9ns
tMISO_fall
MISO fall time
CLOAD=50pF
(48)
9ns
tMISO_valid
MISO valid from clock low
0
15
ns
tMISO_disable
MISO disable time
0
15
ns
CLOAD
MOSI maximum load
200
pF
1.
This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt.
2.
This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple
regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This
typical value allows a raw choose of the external resistor but the definitive choose must be done according to the
recommendations on Chapter 4.1).
3.
Measured between 10% and 90% of output voltage transition.
4.
Measured from a fault detection to 50% of output voltage transition.
5.
Current is defined to be positive when flowing into the pin.
6.
Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This
is to avoid change on output voltage due to heating effect.
7.
Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_FB).
8.
Default state.
9.
The regulated voltage can be calculated using the formula: VSWmain_OUT = VFBREF *(Ra+Rb)/Rb.
Table 5.
Electrical characteristics (continued)
Parameter
Description
Test condition
Min
Typ
Max
Unit



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