MPC8544E datasheet(31/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

Timing diagrams for FIFO appear in Figure 11 and Figure 12.

Figure 11. FIFO Transmit AC Timing Diagram

Figure 12. FIFO Receive AC Timing Diagram

Fall time TX_CLK (80%–20%)

tFITF

—

0.75

—

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN

hold time

tFITDX

0.5

—

3.0

Note:

1. Data valid tFITDV to GTX_CLK Min setup time is a function of clock period and max hold time.

(Min setup = Cycle time – Max hold).

Table 29. FIFO Mode Receive AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

RX_CLK clock period

tFIR

—8.0

—

RX_CLK duty cycle

tFIRH/tFIRH

—

RX_CLK peak-to-peak jitter

tFIRJ

——

250

—

Rise time RX_CLK (20%–80%)

tFIRR

—

0.75

—

Fall time RX_CLK (80%–20%)

tFIRF

—

0.75

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tFIRDV

1.5

—

RX_CLK to RXD[7:0], RX_DV, RX_ER hold time

tFIRDX

0.5

—

Table 28. FIFO Mode Transmit AC Timing Specification (continued)

(continued)At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

tFITF

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITDV

tFITR

tFITH

tFIT

tFITDX

tFIRF

tFIRR

RX_CLK

RXD[7:0]

RX_DV

RX_ER

Valid Data

tFIRDX

tFIRDV

tFIRH

tFIR

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