MPC8544E datasheet(111/117 Pages) FREESCALE

No. de pieza	MPC8544E

Descripción Electrónicos	MPC8544E PowerQUICC III Integrated Processor Hardware Specifications

PDF	117 Pages

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Fabricante Electrónico	FREESCALE [Freescale Semiconductor, Inc]

Página de inicio	http://www.freescale.com

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

111

System Design Information

21.9.1

Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

•TRST should be tied to HRESET through a 0-k

Ω isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 69. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wired onto the system in future debug situations.

•

No pull-up/pull-down is required for TDI, TMS, or TDO.

Figure 68 shows the COP connector physical pinout.

Figure 68. COP Connector Physical Pinout

KEY

No pin

COP_TDO

COP_TDI

COP_RUN/STOP

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

GND

COP_TCK

COP_TMS

COP_SRESET

COP_HRESET

COP_CHKSTP_OUT

MPC8544E Datasheet(PDF) 111 Page - Freescale Semiconductor, Inc