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AS8650

Datasheet - Application In form atio n

1. Cb = capacitance of one bus line in pF.

stages (250ns). This allows for any series protection resistors to be connected between the SDA/SCLK pins and the SDA/SCLK bus

3. I/O pins of Fast-mode devices must not obstruct the SDA and SCLK lines if VLDO1 is switched off.

Characteristics of the SDA and SCLK Bus Lines for F/S Mode I2C Bus.

Table 18. I2C Electrical Parameters

Symbol

Parameter

Standard

Fast

Units

Min

Max

Min

Max

LOW level input voltage:

VLDO1related input levels

0.3V*LDO1

0.3V*LDO1

V

HIGH level input voltage:

VLDO1-related input levels

0.7V*LDO1

0.7V*LDO1

V

Hysteresis of Schmitt trigger input

n/a

n/a

0.05V*LDO1

V

LOW level output voltage (open drain or

open collector) at 3mA sink current

0.4

0.4

V

with a bus capacitance from

10pF to 400pF

250

(see Footnote 2)

(see Footnote 1)

250

(see Footnote 2)

ns

(lab tested

only)

Pulse width of spikes which must be

suppressed by the input filter

n/a

n/a

50

ns

Input current of each I/O pin with an

input voltage between 0.1VLDO1 and

-10

10

-10

(see Footnote 3)

10

(see Footnote 3)

µ

A

Capacitance for each I/O pin

10

10

pF

(guaranteed

by design)

Table 19. I2C Timing Parameters

Symbol

Parameter

Standard

Fast

Units

Min

Max

Min

Max

(see Footnote 1)

SCLK clock frequency

0

100

0

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

4-

0.6

-

µs

LOW period of the SCLK clock

4.7

-

1.3

-

µ

s

HIGH period of the SCLK clock

4.0

-

0.6

-

µ

s

Set-up time for a repeated START

condition

4.7

-

0.6

-

µ

s

Data set-up time

250

-

100

(see Footnote 2)

-ns

Data hold-time

0

(see Footnote 5)

3450

(see Footnote 3)

0

(see Footnote 5)

900

(see Footnote 3)

ns

Rise time of SDA and SCLK signals

-

1000

20+

(see Footnote 4)

300

ns