STM32F407IG datasheet(80/154 Pages) STMICROELECTRONICS

No. de pieza	STM32F407IG

Descripción Electrónicos	USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

PDF	154 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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Electrical characteristics

STM32F405xx, STM32F407xx

80/154

Doc ID 022152 Rev 1

Jitter(5)

Master I2S clock jitter

Cycle to cycle at

12,343 MHz on

48KHz period,

N=432, P=4, R=5

RMS

peak

±280

Average frequency of

12,343 MHz

N=432, P=4, R=5

on 256 samples

TBD

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

400

IDD(PLLI2S)

(6)

PLLI2S power consumption on

VDD

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)

(6)

PLLI2S power consumption on

VDDA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

TBD stands for “to be defined”.

Take care of using the appropriate division factor M to have the specified PLL input clock values.

Guaranteed by design, not tested in production.

Maximum input PLL frequency is recommended for applications sensitive of long term jitter.

Value given with main PLL running.

Based on characterization, not tested in production.

Table 32.

PLLI2S (audio PLL) characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

STM32F407IG Datasheet(PDF) 80 Page - STMicroelectronics

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