HT46R005 datasheet(34/62 Pages) HOLTEK

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HT48R005/HT46R005

Rev. 1.00

November 29, 2011

Control Register Operating Mode

Select Bits for the Pulse Width

Capture Mode

Bit7 Bit6

In this mode the internal clock, fSYS or fSYS/4, is used as

the internal clock for the 8-bit Timer/Event Counter.

However, the clock source, fSYS, for the 8-bit timer is fur-

ther divided by a prescaler, the value of which is deter-

mined

the

Prescaler

Rate

Select

bits

T0PSC2~T0PSC0, which are bits 2~0 in the Timer Con-

trol Register. After the other bits in the Timer Control

bit 4 of the Timer Control Register, can be set high to en-

able the Timer/Event Counter, however it will not actu-

ally start counting until an active edge is received on the

external timer pin.

If the Active Edge Select bit T0EG, which is bit 3 of the

Timer Control Register, is low, once a high to low transi-

tion has been received on the external timer pin, the

Timer/Event Counter will start counting until the external

timer pin returns to its original high level. At this point the

enable bit will be automatically reset to zero and the

Timer/Event Counter will stop counting. If the Active

Edge Select bit is high, the Timer/Event Counter will be-

gin counting once a low to high transition has been re-

ceived on the external timer pin and stop counting when

the external timer pin returns to its original low level. As

before, the enable bit will be automatically reset to zero

and the Timer/Event Counter will stop counting. It is im-

portant to note that in the pulse width capture Mode, the

enable bit is automatically reset to zero when the exter-

nal control signal on the external timer pin returns to its

original level, whereas in the other two modes the en-

able bit can only be reset to zero under program control.

The residual value in the Timer/Event Counter, which

can now be read by the program, therefore represents

the length of the pulse received on the TMR pin. As the

enable bit has now been reset, any further transitions on

the external timer pin will be ignored. The timer cannot

begin further pulse width capture until the enable bit is

set high again by the program. In this way, single shot

pulse measurements can be easily made.

It should be noted that in this mode the Timer/Event

Counter is controlled by logical transitions on the external

timer pin and not by the logic level. When the Timer/Event

Counter is full and overflows, an interrupt signal is gener-

ated and the Timer/Event Counter will reload the value al-

ready loaded into the preload register and continue

counting. The interrupt can be disabled by ensuring that

the Timer/Event Counter Interrupt Enable bit in the corre-

sponding Interrupt Control Register, is reset to zero.

As the TMR pin is shared with an I/O pin, to ensure that

the pin is configured to operate as a pulse width capture

pin, two things have to happen. The first is to ensure that

the Operating Mode Select bits in the Timer Control

width capture Mode, the second is to ensure that the

port control register configures the pin as an input.

Prescaler

Bits T0PSC0~T0PSC2 of the TMRC register can be

used to define a division ratio for the internal clock

source of the Timer/Event Counter enabling longer time

out periods to be setup.

PFD Function

Operating similar to a programmable frequency divider,

the buzzer function within the microcontroller provides a

means of producing a variable frequency output suitable

for applications, such as piezo-buzzer driving or other

interfaces requiring a precise frequency generator.

BZ and BZ pins are a complimentary pair and

pin-shared with I/O pins, PA0 and PA1. The function is

selected via the CTRL0 register, however, if not se-

lected, the pins can operate as normal I/O pins. Note

that the BZ pin is the inverse of the BZ pin generating a

kind of differential output and supplying more power to

connected interfaces such as buzzers. The CTRL0 reg-

ister can select a single BZ pin or the complimentary pair

BZ and BZ. The accompanying table illustrates the truth

table of PA0/BZ and PA1/BZ.

The timer overflow signal is the clock source for the

buzzer circuit. The output frequency is controlled by load-

ing the required values into the timer prescaler and timer

registers to give the required division ratio. The counter

will begin to count-up from this preload register value until

full, at which point an overflow signal is generated, caus-

ing both the BZ and BZ outputs to change state. The

counter will then be automatically reloaded with the

preload register value and continue counting-up.

+ 1

+ 2

+ 3

+ 4

T i m e r

E x t e r n a l T M R

P i n I n p u t

T 0 O N - w i t h T 0 E G = 0

P r e s c a l e r O u t p u t

I n c r e m e n t

T i m e r C o u n t e r

P r e s c a l e r O u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .

Pulse Width Capture Mode Timing Chart (TnEG=0)

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