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Document Number: 66550

S11-1638-Rev. B, 15-Aug-11

Vishay Siliconix

SiC403

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Capacitor Selection

The output capacitors are chosen based on required ESR

and capacitance. The maximum ESR requirement is

controlled by the output ripple requirement and the DC

tolerance. The output voltage has a DC value that is equal to

the valley of the output ripple plus 1/2 of the peak-to-peak

ripple. Change in the output ripple voltage will lead to a

change in DC voltage at the output.

The design goal is that the output voltage regulation be

± 4 % under static conditions. The internal 500 mV reference

tolerance is 1 %. Allowing 1 % tolerance from the FB resistor

divider, this allows 2 % tolerance due to VOUT ripple.

Since this 2 % error comes from 1/2 of the ripple voltage, the

allowable ripple is 4 %, or 42 mV for a 1.05 V output.

The maximum ripple current of 4.4 A creates a ripple voltage

across the ESR. The maximum ESR value allowed is shown

by the following equations.

The output capacitance is usually chosen to meet transient

requirements. A worst-case load release, from maximum

load to no load at the exact moment when inductor current is

at the peak, determines the required capacitance. If the load

release is instantaneous (load changes from maximum to

zero in < 1 µs), the output capacitor must absorb all the

inductor's stored energy. This will cause a peak voltage on

the capacitor according to the following equation.

Assuming a peak voltage VPEAK of 1.150 (100 mV rise upon

load release), and a 10 A load release, the required

capacitance is shown by the next equation.

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 750 mV reference, the DL

output is high and the low-side MOSFET is on. During this

time, the voltage across the inductor is approximately - VOUT.

This causes a down-slope or falling di/dt in the inductor. If the

load dI/dt is not much faster than the - dI/dt in the inductor,

then the inductor current will tend to track the falling load

current. This will reduce the excess inductive energy that

must be absorbed by the output capacitor, therefore a

smaller capacitance can be used.

The following can be used to calculate the needed

capacitance for a given dILOAD/dt:

Peak inductor current is shown by the next equation.

ILPK = IMAX + 1/2 x IRIPPLEMAX

ILPK = 6 + 1/2 x 2.9 = 7.45 A

Rate of change of load current = dILOAD/dt

IMAX = maximum load release = 6 A

Example

This would cause the output current to move from 10 A to

zero in 4 µs as shown by the following equation.

Note that COUT is much smaller in this example, 254 µF

compared to 328 µF based on a worst-case load release. To

meet the two design criteria of minimum 254 µF and

maximum 9 m

 ESR, select two capacitors rated at 150 µF

and 18 m

 ESR.

It is recommended that an additional small capacitor be

placed in parallel with COUT in order to filter high frequency

switching noise.

Stability Considerations

Unstable operation is possible with adaptive on-time

controllers, and usually takes the form of double-pulsing or

ESR loop instability.

Double-pulsing occurs due to switching noise seen at the FB

input or because the FB ripple voltage is too low. This causes

the FB comparator to trigger prematurely after the 250 ns

minimum off-time has expired. In extreme cases the noise

can

cause

three

successive

on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect operation.

This form of instability can usually be avoided by providing

the FB pin with a smooth, clean ripple signal that is at least

10 mVp-p, which may dictate the need to increase the ESR of

the output capacitors. It is also imperative to provide a proper

PCB layout as discussed in the Layout Guidelines section.

ESRMAX =

VRIPPLE

IRIPPLEMAX

ESRMAX = 9.5 m

42 mV

2.9 A

COUT_MIN =

L (IOUT +

x IRIPPLEMAX)2

(VPEAK)2 - (VOUT)2

COUT_MIN =

1.3 µH (6 +

x 2.9)2

(1.15)2 - (1.05)2

COUT_MIN = 328 µF

COUT = ILPK x

L x

x dt

2 (VPK - VOUT)

ILPK

VOUT

IMAX

dlLOAD

Load

dlLOAD

2.5 A

µs

COUT = 7.45 x

1.3 µH x

x 1 µs

2 (1.15 - 1.05)

7.45

1.05

2.5

COUT = 254 µF

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