HT45F23 datasheet(86/152 Pages) HOLTEK

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SPI Communication

After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is

written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer

is complete, the TRF flag will be set automatically, but must be cleared using the application program.

In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD

master should output an SCS signal to enable the slave device before a clock signal is provided. The

slave data to be transferred should be well prepared at the appropriate moment relative to the SCS

signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying

timing diagram shows the relationship between the slave data and SCS signal for various

configurations of the CKPOLB and CKEG bits.

The SPI will continue to function even in the IDLE Mode.

Rev. 1.20

September 15, 2011

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

S C K ( C K P O L B = 1 )

S C K ( C K P O L B = 0 )

S D O

S C S

S D I D a t a C a p t u r e

D 7 / D 0

D 6 / D 1

D 5 / D 2

D 4 / D 3

D 3 / D 4

D 2 / D 5

D 1 / D 6

D 0 / D 7

W r i t e t o S I M D

( S D O d o e s n o t c h a n g e u n t i l f i r s t S C K e d g e )

SPI Slave Mode Timing

- CKEG=0

S C K ( C K P O L B = 1 , C K E G = 0 )

S I M E N , C S E N = 1

S I M E N = 1 , C S E N = 0 ( E x t e r n a l P u l l - H i g h )

S C K ( C K P O L B = 0 , C K E G = 0 )

S C K ( C K P O L B = 1 , C K E G = 1 )

S C K ( C K P O L B = 0 , C K E G = 1 )

S D O ( C K E G = 0 )

S D O ( C K E G = 1 )

S C S

S D I D a t a C a p t u r e

D 7 / D 0

D 6 / D 1

D 5 / D 2

D 4 / D 3

D 3 / D 4

D 2 / D 5

D 1 / D 6

D 0 / D 7

D 7 / D 0

D 6 / D 1

D 5 / D 2

D 4 / D 3

D 3 / D 4

D 2 / D 5

D 1 / D 6

D 0 / D 7

W r i t e t o S I M D

SPI Master Mode Timing

HT45F23 Datasheet(PDF) 86 Page - Holtek Semiconductor Inc

HT45F23 Datasheet(HTML) 86 Page - Holtek Semiconductor Inc

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