CC1021 datasheet(63/94 Pages) TI

63 / 94 page

CC1021

SWRS045C

Page 63 of 87

frequencies is done through the MAIN

included to do the hopping without a need

to re-synchronize the receiver. For more

details refer to Application Note AN014

Frequency Hopping Systems available

from the TI web site.

In order to implement a frequency hopping

system with

CC1021 do the following:

Set the desired frequency, calibrate and

store the following register settings in non-

volatile memory:

STATUS1[3:0]: CHP_CURRENT[3:0]

STATUS2[4:0]: VCO_ARRAY[4:0]

STATUS3[5:0]:VCO_CAL_CURRENT[5:0]

Repeat the calibration for each desired

frequency. VCO_CAL_CURRENT[5:0] is

not dependent on the RF frequency and

the same value can be used for all

frequencies. When performing frequency

hopping, write the stored values to the

corresponding TEST1, TEST2 and TEST3

registers, and enable override:

TEST1[3:0]: CHP_CO[3:0]

TEST2[4:0]: VCO_AO[4:0]

TEST2[5]: VCO_OVERRIDE

TEST2[6]: CHP_OVERRIDE

TEST3[5:0]: VCO_CO[5:0]

TEST3[6]: VCO_CAL_OVERRIDE

CHP_CO[3:0] is the register setting read

from CHP_CURRENT[3:0], VCO_AO[4:0]

the register setting read from

VCO_ARRAY[4:0] and VCO_CO[5:0] is

the

setting

read

from

VCO_CAL_CURRENT[5:0].

Assume channel 1 defined by register

FREQ_A is currently being used and that

CC1021 should operate on channel 2 next

(to change channel simply write to register

MAIN[6]). The channel 2 frequency can be

set by register FREQ_B which can be

written to while operating on channel 1.

The calibration data must be written to the

TEST1-3 registers after switching to the

next frequency. That is, when hopping to a

new channel write to register MAIN[6] first

and the test registers next. The PA should

be switched off between each hop and the

PLL should be checked for lock before

switching the PA back on after a hop has

been performed.

Note

that

the

override

bits

VCO_OVERRIDE, CHP_OVERRIDE and

VCO_CAL_OVERRIDE must be disabled

when performing a re-calibration.

24.

PCB Layout Recommendations

The top layer should be used for signal

routing, and the open areas should be

filled with metallization connected to

ground using several vias.

The area under the chip is used for

grounding and must be connected to the

bottom ground plane with several vias. In

the TI reference designs we have placed 9

vias inside the exposed die attached pad.

These vias should be “tented” (covered

with solder mask) on the component side

of the PCB to avoid migration of solder

through the vias during the solder reflow

process.

Do not place a via underneath

CC1021 at

“pin #1 corner” as this pin is internally

connected to the exposed die attached

pad, which is the main ground connection

for the chip.

Each decoupling capacitor should be

placed as close as possible to the supply

pin it is supposed to decouple. Each

decoupling capacitor should be connected

to the power line (or power plane) by

separate vias. The best routing is from the

power line (or power plane) to the

decoupling capacitor and then to the

CC1021 supply pin. Supply power filtering

is very important, especially for pins 23,

22, 20 and 18.

Each decoupling capacitor ground pad

should be connected to the ground plane

using a separate via. Direct connections

between neighboring power pins will

increase noise coupling and should be

avoided unless absolutely necessary.

The external components should ideally

be as small as possible and surface mount

devices are highly recommended.

CC1021 Datasheet(PDF) 63 Page - Texas Instruments

CC1021 Datasheet(HTML) 63 Page - Texas Instruments

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