ADE7880 datasheet(93/104 Pages) AD

93 / 104 page

Data Sheet

ADE7880

Rev. A| Page 93 of 104

Bit

Mnemonic

Default Value

Description

REVPSUM3

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in

the CF3 data path changes sign.

HREADY

When this bit is set to 1, it enables an interrupt when the harmonic block output

registers have been updated. If Bit 1 (HRCFG) in HCONFIG register is cleared to 0, the

interrupt is triggered every time the harmonic calculations are updated at 8 kHz

rate. If Bit HRCFG is set to 1, the interrupt is triggered every time the harmonic

calculations are updated at 8 kHz rate starting 750 ms after the harmonic block

setup.

31:19

Reserved

00 0000 0000

0000

Reserved. These bits do not manage any functionality.

Table 39. MASK1 Register (Address 0xE50B)

Bit

Mnemonic

Default Value

Description

NLOAD

When this bit is set to 1, it enables an interrupt when at least one phase enters no

load condition determined by the total active power and VNOM based apparent

power.

FNLOAD

When this bit is set to 1, it enables an interrupt when at least one phase enters no

load condition based on fundamental active and reactive powers.

VANLOAD

When this bit is set to 1, it enables an interrupt when at least one phase enters no

load condition based on apparent power.

ZXTOVA

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A

voltage is missing.

ZXTOVB

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B

voltage is missing.

ZXTOVC

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C

voltage is missing.

ZXTOIA

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A

current is missing.

ZXTOIB

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B

current is missing.

ZXTOIC

When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C

current is missing.

ZXVA