ADMP441 datasheet(4/16 Pages) AD

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ADMP441

Data Sheet

Rev. A | Page 4 of 16

I²S DIGITAL INPUT/OUTPUT

–40°C < TA < +85°C, 1.8 V < VDD < 3.3 V, unless otherwise noted.

Table 2.

Limit1

Parameter

Symbol

Test Conditions/Comments

Min

Max

Unit

DIGITAL INPUT

Voltage Input Low (L/R, WS, SCK)

VIL

0.25 × VDD

Voltage Input High (L/R, WS, SCK)

VIH

0.7 × VDD

VDD

SD DIGITAL OUTPUT

Voltage Output Low

VOL

VDD = 1.8 V, ISINK = 0.25 mA

0.1 × VDD

Voltage Output Low

VOL

VDD = 1.8 V, ISINK = 0.7 mA

0.3 × VDD

Voltage Output High

VOH

VDD = 1.8 V, ISINK = 0.7 mA

0.7 × VDD

Voltage Output High

VOH

VDD = 1.8 V, ISINK = 0.25 mA

0.9 × VDD

Voltage Output Low

VOL

VDD = 3.3 V, ISINK = 0.5 mA

0.1 × VDD

Voltage Output Low

VOL

VDD = 3.3 V, ISINK = 1.7 mA

0.3 × VDD

Voltage Output High

VOH

VDD = 3.3 V, ISINK = 1.7 mA

0.7 × VDD

Voltage Output High

VOH

VDD = 3.3 V, ISINK = 0.5 mA

0.9 × VDD

1 Limits based on characterization results; not production tested.

Table 3. Serial Data Port Timing Specifications

Parameter

Description

Min

Max

Unit

tSCH

SCK high

tSCL

SCK low

tSCP

SCK period

312

fSCK

SCK frequency

0.5

3.2

MHz

tWSS

WS setup

tWSH

WS hold

fWS

WS frequency

7.8

49.3

kHz

TIMING DIAGRAM

SCK

tSCP

tSCH

tSCL

tWSH

tWSS

Figure 3. Serial Data Port Timing

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