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LTC3589 Datasheet(PDF) 33 Page - Linear Technology

No. de pieza LTC3589
Descripción Electrónicos  8-Output Regulator with Sequencing and I2C
PDF  50 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
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LTC3589 Datasheet(HTML) 33 Page - Linear Technology

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LTC3589/LTC3589-1/
LTC3589-2
33
3589fe
Figure 14. PGOOD Pin and PGSTAT Status Register Timing
VOUTx
PGOOD
IRQ
3589 F14
ENx
200μs
25μs
25μs
1sec
14ms
250μs
250μs
ENABLE
DISABLE
UNDERVOLTAGE
DISABLED IF
WAKE LOW
WAKE HIGH AFTER 1sec
IF PWR_ON HIGH
EXTENDED
UNDERVOLTAGE
(FAULT)
WAKE
250μs
Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing
RSTO Pin Function
The RSTO (reset output) pin is an open-drain output for use
as a power-on reset signal. It is pulled LOW at initial power
until LDO1 is within 8% of its target and the initial one second
start-uptimerisfinished.RSTOremainsHIGHduringnormal
operation and will be pulled low if LDO1 loses regulation for
more than 25μs or a pushbutton hard reset is initiated. RSTO
is released high 14ms after LDO1 returns to regulation.
Figure 13 shows a initial power-up for the RSTO pin. If VIN
is not above its undervoltage thresholds at the end of the 1
second start-up time, the IRQ pin will be pulled LOW and an
undervoltage bit will be set in the IRQSTAT status register.
voltage for longer than 25μs (typical), the PGOOD pin is
pulled LOW and the appropriate bit in the PGSTAT status
register (Table 15) is set.
Table 15. PGSTAT Read-Only Register Bit Definitions
PGSTAT[BIT] VALUE
SETTING
00
1
LDO1_STBY Output Low
LDO1_STBY Output Good
10
1
Step-Down Switching Regulator 1 Output Low
Step-Down Switching Regulator 1 Output Good
20
1
Step-Down Switching Regulator 2 Output Low
Step-Down Switching Regulator 2 Output Good
30
1
Step-Down Switching Regulator 3 Output Low
Step-Down Switching Regulator 3 Output Good
40
1
Buck-Boost Regulator 4 Output Low
Buck-Boost Regulator 4 Output Good
50
1
LDO2 Output Low
LDO2 Output Good
60
1
LDO3 Output Low
LDO3 Output Good
70
1
LDO4 Output Low
LDO4 Output Good
Figure 14 shows the PGOOD pin and PGSTAT status reg-
ister timing. When no regulator is enabled, the PGOOD
pin is pulled LOW and PGSTAT bits are LOW. PGOOD and
the PGSTAT bits are HIGH 250μs after the last enabled
regulator is within 7% of its target.
PGOOD Pin and PGSTAT Status Register Function
Each LTC3589 regulator has an internal power good out-
put that is active whenever the regulators feedback pin is
closer than 7% (typical) from its input reference voltage.
If any of the internal power good signals indicate a low
OPERATION
LDO1
RSTO
VIN 2.7V
–8%
1 SEC
INITIAL POWER-UP
LTC3589
LDO1 UNDERVOLTAGE
25μs
14ms
3589 F13
LDO1
RSTO
VIN
–8%
INITIAL POWER-UP
LTC3589-1/LTC3589-2
LDO1 UNDERVOLTAGE
25μs
14ms
14ms



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