SP6200 datasheet(7/10 Pages) SIPEX

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Date:5/25/04

SP6200/6201 100/200mA CMOS LDO Regulator

An accurate Vout good indicator is provided on

all the fixed output version devices, pin 4 (RSN),

Figure 1. This is an open drain, logic output that

can be used to hold a microprocessor or micro-

controller in a RESET condition when it's power

supplied by Vout is 4% out of nominal regula-

tion. A 1% hysteresis is included in the Reset

Not function, so that false alarms are not issued

as a result of LDO's output noise. The Reset Not

function reacts in 10 to 50

µs.

Adjustable Output Version

The adjustable version can be programmed to

any voltage from 2.7V to 6V for the industrial

temperature range; 2.5V to 6V for the commer-

cial temperature range. The output can not be

programmed below 2.5V due a headroom re-

striction. Since the bandgap is bootstrapped to

the output, the output voltage must be above the

minimum bandgap supply voltage. The bandgap

requires 2.7V or greater at -40

°C and requires

2.5V or greater at 0

°C.

The regulator's output can be adjusted to a

specific output voltage by using two external

resistors, Figure 2. The resistor's set the output

voltage based on the following equation:

VOUT = 1.25 (R2/R1 + 1)

Resistor values are not critical because the ADJ

node has a high input impedance, but for best

results use resistors of 470k

Ω or less. A capaci-

tor from ADJ to Vout pin provides improved

noise performance as is shown in the following

plot.

Noise Performance 10Hz to 100kHz

Adj, Vin = 4.3V, Vout = 3.3V (Cin = Cout = 1uF)

100

200

300

400

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

Bypass Cap from Vout to FB (pF)

THEORY OF OPERATION: Continued

Reset Not (VOUT good) Output

Input Capacitor

A small capacitor, 1

µF or higher, is required

from VIN to GND to create a high frequency

bypass for the LDO amplifier. Any ceramic or

tantalum capacitor may be used at the input.

Capacitor ESR (effective series resistance)

should be smaller than 3

Ω.

Output Capacitor

An output capacitor is required between VOUT

and GND to prevent oscillation. A capacitance

as low as 0.22

µF can fulfill stability require-

ments in most applications. A 1

µF capacitor

will ensure unconditional stability from no load

to full load over the entire input voltage, output

voltage and temperature range. Larger capacitor

values improve the regulator's transient response.

The output capacitor value may be increased

without limit. The output capacitor should have

an ESR (effective series resistance) below 5

Ω

and a resonant frequency above 1MHz.

No Load Stability

The SP6200/6201 will remain stable and in

regulation with no external load (other than the

internal voltage driver) unlike many other volt-

age regulators. This is especially important in

CMOS RAM keep-alive applications.

Thermal Considerations

The SP6200 is designed to provide 100mA of

continuous current, while the SP6201 will pro-

vide 200mA of continuous current. Maximum

power dissipation can be calculated based on the

output current and the voltage drop across the

part. To determine the maximum power dissipa-

tion in the package, use the junction-to-ambient

thermal resistance of the device and the follow-

ing basic equation:

PD =

(TJ(max) - TA)

θJA

TJ(max) is the maximum junction temperature of

the die and is 125

°C. TA is the ambient operating.

θJA is the junction-to-ambient thermal resistance

for the regulator and is layout dependent.

The actual power dissipation of the regulator

circuit can be determined using one simple

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