SL74HC4015D datasheet(4/6 Pages) SLS

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SL74HC4015

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figure 2)

2.0

4.5

6.0

4.8

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q (Figures

2 and 5)

2.0

4.5

6.0

175

220

265

tPHL

Maximum Propagation Delay, Reset to Q (Figures

1 and 5)

2.0

4.5

6.0

205

255

310

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 3 and 5)

2.0

4.5

6.0

110

CIN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Latch)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption: PD=CPDVCC

2f+I

CCVCC

140

TIMING REQUIREMENTS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tsu

Minimum Setup Time, D to Clock

(Figure 4)

2.0

4.5

6.0

9.0

Minimum Hold Time, Clock to D

(Figure 4)

2.0

4.5

6.0

trec

Minimum Recovery Time, Reset to

Clock (Figure 1)

2.0

4.5

6.0

Minimum Pulse Width, Reset (Figure

2.0

4.5

6.0

100

120

Minimum Pulse Width, Clock (Figure

2.0

4.5

6.0

100

120

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

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