SL74HC595 datasheet(7/10 Pages) SLS

7 / 10 page

SL74HC595

System Logic

Semiconductor

SLS

FUNCTION TABLE

Inputs

Resulting Function

Operation

Reset Serial

Input

Shift

Clock

Latch

Clock

Output

Enable

Shift

Contents

Latch

Contents

Serial

Output

SQH

Parallel

Outputs

QA-QH

Reset shift register

L,H,

Shift data into shift

L,H,

SRA

SRN SRN+1

SRG SRH

Shift register remains

unchanged

L,H,

Transfer shift register

contents to latch

L,H,

SRN LRN

SRN

Latch register remains

unchanged

L,H,

Enable parallel

outputs

Enabled

Force outputs into

high-impedance state

SR = shift register contents

X = don’t care

LR = latch register contents

Z = high impedance

D = data (L,H) logic level

* = depends on Reset and Shift Clock inputs

U = remains unchanged

** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTS:

A - Serial Data Input. The data on this pin is shifted

into the 8-bit serial shift register.

CONTROL INPUTS:

Shift Clock - Shift Register Clock Input. A low-to-

high transition on this input causes the data at the

Serial Input pin to be shifted into the 8-bit shift

Reset - Active-low, Asynchronous, Shift Register

Reset Input. A low on this pin resets the shift

is not affected.

Latch Clock - Storage Latch Clock Input. A low-to-

high transition on this input latches the shift

Output Enable - Active-Low Output Enable. A low

on this input allows the data from the latches to

bepresented at the outputs. A high on this input

forces the outputs (QA-QH) into the high-impedance

state. The serial output is not affected by this

control unit.

OUTPUTS:

QA-QH - Noninverted, 3-state, latch outputs.

SQH - Voninverted, Serial Data Output. This is the

output of the eighth stage of the 8-bit shift register.

This output does not have three-state capability.

SL74HC595 Datasheet(PDF) 7 Page - System Logic Semiconductor

SL74HC595 Datasheet(HTML) 7 Page - System Logic Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10

Datasheet Descarga

Enlace URL