SM320C30 datasheet(2/48 Pages) TI1

2 / 48 page

SMJ320C30

DIGITAL SIGNAL PROCESSOR

SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

description (continued)

AB C D E F G H J K L M N P R

181-Pin GB Grid Array Package

(BOTTOM VIEW)

196-Pin HFG Quad Flatpack

(TOP VIEW)

DVDD DVSS

DVSS DVDD

147

The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single

cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,

internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.

High performance and ease of use are results of these features.

General-purpose applications are enhanced by the large address space, multiprocessor interface, internally

and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple

interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to

dedicated coprocessor.

High-level language support is implemented easily through a register-based architecture, large address space,

powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

For additional information when designing for cold temperature operation, please see Texas Instruments

application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature

number SGUA001.

SM320C30 Datasheet(PDF) 2 Page - Texas Instruments