TNETE2008

OctalPHY

EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS042B – DECEMBER 1997 – REVISED JUNE 1998

25

POST OFFICE BOX 655303

LED drive timing

To sample this interface, count 32 clocks from the falling edge of RESET, and take samples every 32 clocks

(1600 ns) thereafter. Sampling is shown in Table 2.

LED drive (see Figure 14)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

1

td(Sample X)

Delay time from RESET

↓ to S0 active

625

750

ns

2

tw(Sample X)

Pulse duration (see Notes 12 and 13)

1600

ns

NOTES: 12. LED interface runs synchronously to CLK signal, 32 clocks/sample at constant numbers of CLK periods. Phase of CLK, relative to

LSEL transitions, is not controlled.

13. Active low for odd channels and active high for even channels

2

2

RESET

(input)

LSEL 0,2,4,6

LSEL 1,3,5,7

(outputs)

1

CLK

32 Clocks

32 Clocks

Sample 0

Sample 1

Figure 14. LED Drive Timing

Table 2. LED Drive Timing

SAMPLE

(SEE NOTE 14)

LSEL0,1

LSEL2,3

LSEL4,5

LSEL6,7

0

link1

link3

link5

link7

1

active0

active2

active4

active6

2

dupcol0

dupcol2

dupcol4

dupcol6

3

link0

link2

link4

link6

4

active1

active3

active5

active7

5

dupcol1

dupcol3

dupcol5

dupcol7

6

(same as sample 0)

link1

link3

link5

link7

7

(same as sample 1)

active0

active2

active4

active6

NOTE 14: In general, sample (n) = sample (n + 6), sample (n – 6).