Integrated Silicon Solution, Inc. — www.issi.com

13

Rev. A

05/14/2012

1

2

3

4

5

6

7

8

9

10

11

12

IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,

IS64WV3216DBLL/DBLS

-20 ns

-25 ns

-35 ns

-45ns

Symbol Parameter

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Unit

WriteCycleTime

20—

25—

35—

45—

ns

CE

toWriteEnd

12—

18—

25—

35—

ns

AddressSetupTime

12—

15—

25—

35—

ns

toWriteEnd

AddressHoldfromWriteEnd0—

0—

0—

0—

ns

AddressSetupTime

0—

0—

0—

0—

ns

LB

,UBValidtoEndofWrite

12—

18—

30—

35—

ns

WE

PulseWidth(OE=HIGH)12—

18—

30—

35—

ns

WE

PulseWidth(OE=LOW)17—

20—

30—

35—

ns

DataSetuptoWriteEnd

9—

12—

15—

20—

ns

DataHoldfromWriteEnd

0—

0—

0—

0—

ns

—9

—12

—20

—20

ns

3—

5—

5—

5—

ns

Notes:

1. TestconditionsforIS61WV3216LLassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulse

2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandUBorLB,andWELOW.Allsignalsmustbeinvalidstatesto

initiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtothe

risingorfallingedgeofthesignalthatterminatesthewrite.