STULPI01A_12 datasheet(22/44 Pages) STMICROELECTRONICS

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Block description

STULPI01A, STULPI01B

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Doc ID 14817 Rev 4

6.14

Car Kit (UART) mode

This mode is entered by writing to the Car Kit mode bit in the interface control register. The

STULPI01 does not implement all features of Car Kit mode, only the UART functionality is

preserved.

TXD or RXD paths are activated only when the corresponding bits TXD_EN/RXD_EN in car

kit control register bits (Table 23) are set.

The UART_2V7 bit controls the voltage level of UART signaling. If 2V7 volt signaling is used,

after the UART mode is entered, PLL is disabled and the voltage on the regulator output

starts to decrease to 2.7 V. After a time marked as tUARTON2V7, the TXD output on the USB

bus is enabled.

When leaving Car Kit mode, TXD is disabled immediately when the STP pin is asserted.

The time required to exit Car Kit mode is equivalent to the time needed for PLL startup.

When 3.3 volt UART signaling is selected, the TXD line is enabled immediately after

entering Car Kit mode, and disabled after exiting this mode.

Note:

When Car Kit mode is used with 2V7 signaling, the PLL and output clock are always

stopped regardless of the setting of the ClockSuspendM bit.

6.15

Low-power mode

The STULPI01 enters Low-power mode when the SuspendM bit in the interface control

the full wake-up capability as defined in the ULPI specification is still maintained.

When in Low-power mode, the PHY drives D3-D0 with the signals listed in Table 11. Line

state is driven combinatorially from the SE receivers. The INT signal is asserted whenever

any unmasked interrupt occurs. The PHY latches interrupt events directly from analog

circuitry because the clock is powered down.

Table 10.

Car kit signals mapping

Default car kit signals mapping (UART_DIR = 0)

Signal

ULPI lines

USB lines

TXD

DATA[0] (input)

DM (output)

RXD

DATA[1] (output) <-

DP (input)

Reserved

DATA[2] (input)

INT

DATA[3] (output)

Car kit signals mapping (UART_DIR = 1)

Signal

ULPI lines

USB lines

TXD

DATA[0] (input)

DP (output)

RXD

DATA[1] (output) <-

DM (input)

Reserved

DATA[2] (input)

INT

DATA[3] (output)

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