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STA333W Datasheet(PDF) 28 Page - STMicroelectronics |
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STA333W Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 49 page ![]() Register description STA333W 28/49 Doc ID 13365 Rev 2 Overcurrent warning detect adjustment bypass The status bit OCWARN is used to warn of an overcurrent condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default -3dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning volume adjustment is applied, it remains applied until the device is reset. The overcurrent limit can be changed via register OLIM (Output limit register (addr 0x34) on page 38). 6.1.4 Configuration register D (addr 0x03) Zero-detect mute enable Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fS) then that individual channel is muted if this function is enabled. 6.1.5 Configuration register E (addr 0x04) Max power correction variable Table 23. Overcurrent warning detect adjustment bypass Bit R/W RST Name Description 7R/W 1OCRB 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled D7 D6 D5 D4 D3 D2 D1 D0 Reserved ZDE Reserved 01 00 000 0 Table 24. Zero detect mute enable Bit R/W RST Name Description 6 R/W 1 ZDE 1: enable the automatic zero-detect mute D7 D6 D5 D4 D3 D2 D1 D0 SVE ZCE DCCV PWMS AME NSBW MPC MPCV 11 00 001 0 Table 25. Max power correction variable Bit R/W RST Name Description 0R/W 0MPCV 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient |
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