WM8728

Production Data

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PD, Rev 4.6, August 2008

24

SELECTION OF LRCIN POLARITY

this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 10,

Figure 11 and Figure 12. Note that if this feature is used as a means of swapping the left and right

channels, a 1 sample phase difference will be introduced.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

Interface Control

1

LRP

0

LRCIN Polarity (normal)

0 : normal LRCIN polarity

1: inverted LRCIN polarity

Table 16 LRCIN Polarity Control

In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure

13 and Figure 14.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

Interface Control

1

LRP

0

DSP Format (DSP modes)

0 : Late DSP mode

1: Early DSP mode

Table 17 DSP Format Control

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that

detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the BCKIN

rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed

between the data words. The word order is DIN left, DIN right.

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left

and right channel DACs from the next audio input sample. No update to the attenuation registers

is required for ATC to take effect.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

Interface Control

2

ATC

0

Attenuator Control Mode:

0 : Right channels use Right

attenuation

1:

Right Channels use Left

Attenuation

Table 18 Attenuation Control Select

OUTPUT PHASE REVERSAL

The REV register bit controls the phase of the output signal. Setting the REV bit causes the

phase of the output signal to be inverted.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

Interface Control

4

REV

0

Analogue Output Phase

0: Normal

1: Inverted

Table 19 Output Phase Control

BCKIN POLARITY

By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change

on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can

be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the

inverse of that shown in Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0011

Interface Control

5

BCP

0

BCKIN Polarity

0 : normal BCKIN polarity

1: inverted BCKIN polarity

Table 20 BCKIN Polarity Control