WM8978CGEFLSLASHV datasheet(94/118 Pages) WOLFSON

94 / 118 page

WM8978

Production Data

PD, Rev 4.5, October 2011

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

4:2

BCLKDIV

000

Configures the BCLK output frequency, for use

when the chip is master over BCLK.

000=divide by 1 (BCLK=SYSCLK)

001=divide by 2 (BCLK=SYSCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Digital Audio

Interfaces

Reserved

Sets the chip to be master over LRC and BCLK

0=BCLK and LRC clock are inputs

1=BCLK and LRC clock are outputs generated

by the WM8978 (MASTER)

Digital Audio

Interfaces

7 (07h)

8:4

00000

Reserved

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Audio Sample

Rates

SLOWCLKEN

Slow clock enable. Used for both the jack insert

detect debounce circuit and the zero cross

timeout.

0 = slow clock disabled

1 = slow clock enabled

Analogue

Outputs

8 (08h)

8:6

000

Reserved

5:4

OPCLKDIV

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

General

Purpose

Input/Output

(GPIO)

GPIO1POL

GPIO1 Polarity invert

0=Non inverted

1=Inverted

General

Purpose

Input/Output

(GPIO)

2:0

GPIO1SEL

[2:0]

000

CSB/GPIO1 pin function select:

000= input (CSB/jack detection: depending on

MODE setting)

001= reserved

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=logic 1

111=logic 0

General

Purpose

Input/Output

(GPIO)

WM8978CGEFL/V Datasheet(PDF) 94 Page - Wolfson Microelectronics plc

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