AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001

Page 11 of 18

The following table specifies the timing parameters relating to fig. 3:

6\PERO

3DUDPHWHU

PLQ

PD[

8QLW

1RWH

tSTB

Delay PSTBn HL-edge to Px

output data valid

1.5

µs

tPSTBn

PSTBn strobe width

6

6.8

µs

1

tINP

Input data valid time window

10.5

12.5

µs

2

Notes:

1

Pulse width depends substantially on value of external pull-up resistor

2

Timing reference is PSTBn HL-edge.

Applies only to parameter port set to 'input' operation

The dc-parameters of the parameter port pins P3, …, P0 are specified as follows:

6\PERO

3DUDPHWHU

PLQ

PD[

8QLW

1RWH

IOUTLO

Sink current @ output L

10

mA

VOUT = 1V

IOUTHI

Leakage current @ output off

- 10

10

µA

VOUT = 5V

IOUTHI7

Leakage current @ output off;

pull-up current source off

- 1

1

µA

VOUT = 5V;

IO-conf. = 7

IINLO

Input current @ VIN = 1V

- 5

- 20

µA

1

VSCHLT

Input threshold voltage

2.5

3.5

V

2

VIN

Acceptable input voltage @

output off

- 0.3

40

V

Notes:

1

The passive high-side current-source provides an about constant input current @

0V <= VIN <= 4V

2

No hysteresis implemented

Though equipped for bidirectional data transfer as D3, …, D0, the parameter port is never-

theless less flexible than the data port.

Note the following differences:

ik) The parameter port is set portwise, the data port bitwise by the IO-configuration code;

il) The parameter port can only be set to either ‘output’ or ‘input’. A bidirectional behaviour

within a strobe cycle is not possible;

im) The parameter port is set to ‘output’ as a rule; the only exception occurs in case of IO-

configuration 7 and a master data request, which set it to ‘input’.

To govern the data transfer at the parameter port P3, …, P0 strobe pin PSTBn is equipped

with a low-side open-drain output switch plus a passive high-side current source with a nom.

10 µA pull-up current capability. Typically the PSTBn-strobe width is about 6 µs, see fig. 3.

( However to simplify and shorten the component test time of the slave device, the PSTBn pin

is also used as an input. Input low pulses of more than 50 µs each will step and cycle the de-

vice through 3 different testmodes beyond the regular operation as described in this da-

tasheet.)