AD7008 datasheet(6/16 Pages) AD

6 / 16 page

REV. B

–6–

AD7008

AND

CONTROL

LOGIC

PHASE

ACCUMULATOR

ACCUM RESET

SLEEP

AM ENABLE

PHASE

SUMMATION

SIN

COS

ROM

DAC

SIN/ COS

SUMMATION

11 PIPELINE DELAYS

13 PIPELINE DELAYS

9:0 19:10

IOUT/

IOUT

14 PIPELINE DELAYS

Figure 7. AD7008 CMOS DDS Modulator (See Table I)

CS (27)

D0-D15

(19-26, 8-15)

TC0-TC3

ACCUMULATOR

RESET

CLK

D Q

x 6

D Q

x 6

PASS

x 6

CLK

LOAD (36)

FSEL (31)

(32-35)

CLK

RESET (38)

RESET SYNCHRONIZATION

TRANSFER CONTROL (TC) REGISTER

CLK

D Q

x 5

TC0

TC1

LOAD

TC3

TC2

D Q

TC3

TC2

D Q

x 20

FREQ 0

FREQ 1

FREQUENCY

REGISTERS

PHASE REGISTER

D Q

x 12

CLK

D Q

x 32

IQ MOD REGISTER

x32

TO PHASE

SUMMATION

TO SIN/COS

SUMMATION

TO PHASE

ACCUMULATOR

CLK

TRANSFER DECODE

FSELECT

CLOCK (30)

x 5

D FLIP-FLOPS ARE MASTER SLAVE,

LATCHING DATA ON CLK RISING EDGE.

CLK

x 24

WR (16)

SCLK (41)

SDATA (42)

SLEEP (37)

15:0 23:8

15:8 7:0

23:0

7:0

D Q

x 32

32-BIT SERIAL

ASSEMBLY REGISTER

32-BIT PARALLEL

ASSEMBLY REGISTER

x 32

MUX

31:0

x 4

CLK

3:0

x 32

BUS MODE

SYNCHRO LOGIC

CLK

AM ENABLE

SLEEP

COMMAND REGISTER

CLK

PASS FLIP-FLOPS ARE TRANSPARENT

WHEN THE CLOCK IS LOW.

CLK

31:8

D Q

x 32

Figure 8. AD7008 Register and Control Logic

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