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AD7011ARS Datasheet(PDF) 5 Page - Analog Devices |
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AD7011ARS Datasheet(HTML) 5 Page - Analog Devices |
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5 / 12 page ![]() AD7011 REV. B –5– ANALOG MODE TIMING Parameter Limit at TA = –40°C to +85°C Units Description t20 15 ns min MCLK Rising Edge to FRAME Setup Time. t21 15 ns min MCLK Rising Edge to FRAME Hold Time. 15t1 ns max t22 16t1 ns FRAME Cycle Time. t23 15 ns min MCLK Rising Edge to Data Setup Time. t24 15 ns min MCLK Rising Edge to Data Hold Time. (VAA = VDD = +5 V 10%. AGND = DGND = 0 V. All specifications are TMIN to TMAX unless otherwise noted.) MCLK t 20 FRAME I DATA DB9 DB8 DB1 DB0 DB9 DB8 DB7 Q DATA DB9 DB8 DB1 DB0 DB9 DB8 DB7 t 23 t 24 t 21 t 22 Figure 6. Analog Mode Serial Interface Timing Q I MODULAR OUTPUT DURING FTEST Figure 7. Modulator State During FTEST Table I. MODE 1 MODE 2 Operation 0 0 Digital TIA Mode 1 0 Analog Mode 0 1 FTEST 1 1 Factory Test, Reserved Table II. Mode of Operation MODE 1 MODE 2 MCLK Digital Bit Rate DAC Update Rate Digital Mode 0 0 3.1104 MHz 48.6 kHz N/A Analog Mode 1 0 2.56 MHz N/A 160 kHz |
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