REV. 0

AD7664

–13–

of power supply sequencing and thus free from supply voltage

induced latchup. Additionally, it is very insensitive to power supply

variations over a wide frequency range as shown in Figure 9.

–50

1

INPUT FREQUENCY – kHz

1000

–60

–70

–80

100

–55

–65

–75

10

Figure 9. PSRR vs. Frequency

POWER DISSIPATION VS. THROUGHPUT

Operating currents are very low during the acquisition phase,

which allows a significant power saving when the conversion

rate is reduced as shown in Figure 10. This power saving depends

on the mode used. In impulse mode, the AD7664 automatically

reduces its power consumption at the end of each conversion

phase. This feature makes the AD7664 ideal for very low power

battery applications. It should be noted that the digital inter-

face remains active even during the acquisition phase. To reduce

the operating digital supply currents even further, the digital

inputs need to be driven close to the power supply rails (i.e.,

DVDD or DGND for all inputs except EXT/

INT, INVSYNC,

INVSCLK, RDC/SDIN, and OVDD or OGND for these last

four inputs).

100k

0.1

SAMPLING RATE – SPS

100k

1k

10

1

100

10k

1M

10k

1k

100

10

1

0.1

WARP/NORMAL

IMPULSE

Figure 10. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conversion

process. The AD7664 is controlled by the signal

CNVST which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The

CNVST signal operates independently of

CS and RD signals.

CNVST

BUSY

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

Figure 11. Basic Conversion Timing

In impulse mode, conversions can be automatically initiated. If

CNVST is held low when BUSY is low, the AD7664 controls the

acquisition phase and then automatically initiates a new conver-

sion. By keeping

CNVST low, the AD7664 keeps the conversion

process running by itself. It should be noted that the analog

input has to be settled when BUSY goes low. Also, at power-up,

CNVST should be brought low once to initiate the conversion

process. In this mode, the AD7664 could sometimes run slightly

faster then the guaranteed limits in the impulse mode of 444 kSPS.

This feature does not exist in warp or normal modes.

RESET

DATA

BUSY

CNVST

Figure 12. RESET Timing

Although

CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

For applications where the SNR is critical,

CNVST signal

should have a very low jitter. Some solutions to achieve that is

to use a dedicated oscillator for

CNVST generation or, at least,

to clock it with a high-frequency low-jitter clock as shown in

Figure 5.